A multi-core processor can drive a plurality of processes at the same time using a plurality of cores. Transistor integration of a single chip is increasing rapidly according to Moore's law, but it is hard to enhance single-core performance due to limitations such as power. Hence, a multi-core architecture appears and is widely used, and the multi-cores share a last level cache in such a system. When several processes run at the same time in such a multi-processor environment, the processes begin to interfere with their caching data because they share the last level cache. Thus, the processes compete for the last level cache in order to occupy the last level cache and cause cache pollution. There are several conventional techniques developed to avoid the pollution of the last level cache between the processes. However, the conventional techniques mostly apply a static cache partitioning scheme by obtaining the number of cache lines to be given to each process through profiling, or consider only a situation when two processes are executed together, rather than the multiple processes, and does not apply processes features which dynamically change. Also, the conventional techniques used a simulator, rather than developing in an actual environment, or were developed with hardware support of Field-Programmable Gate Array (FPGA).
The conventional techniques used a hardware approach, rather than a software approach, which directly accesses a memory without going through the cache or partitions the cache using the number of sets. Although implemented with the software approach, it is necessary to analyze performance variation of the process according to a cache size through several profilings before the process execution in order to allocate an optimal cache space between the processes, and this method has difficulty in reflecting a cache use pattern of the process dynamically changing. Also, since every process requires a minimum cache size, when a plurality of processes splits a small shared cache to their isolated cache space, the performance can be further degraded than sharing the small shared cache by the processes. Accordingly, most of the conventional techniques contain limitations of limiting the number of the executed processes to two.